Application of seed and plate metallization to 15.6cm × 15.6cm IBC cells

Published: September 1, 2015

By Sukhvinder Singh, imec, Leuven, Belgium; Barry O’Sullivan, imec, Leuven, Belgium; Manabu Kyuzo, Kyocera Corporation, Kyoto, Japan; Shruti Jambaldinni, imec, Leuven, Belgium; Loic Tous, imec, Leuven, Belgium; Richard Russell, imec, Leuven, Belgium; Maarten Debucquoy, imec, Leuven, Belgium; Jozef Szlufcik, imec, Leuven, Belgium; Jef Poortmans, imec, Leuven, Belgium; KU Leuven, Belgium; University of Hasselt, Belgium

Interdigitated back contact (IBC) Si solar cells can be highly efficient: record efficiencies of up to 25.0%, measured over a cell area of 121cm2, have been demonstrated on IBC solar cells by SunPower. The high efficiencies achieved can be attributed to several advantages of cells of this type, including the absence of front metal grid shading and a reduced series resistance. Several metallization schemes have been reported for IBC cells, including screen-printing pastes, and physical vapour deposition (PVD) metal and Cu plating with a suitable barrier layer. In the IBC process development at imec, upscaling from small-area 2cm × 2cm cells to full-area 15.6cm × 15.6cm cells was carried out. In the first instance the 3μm-thick sputtered Al metallization scheme from the 2cm × 2cm cells was adopted. This resulted in cell efficiencies of up to 21.3%, limited by a fill factor (FF) of 77.4%. Besides the limited conductivity of this metallization, the sputtering of a thick Al layer is not straightforward from an industrial perspective; moreover, an Al cell metallization cannot be easily interconnected during module fabrication. A Cu-plating metallization for the large-area IBC cells was therefore investigated, and the scheme is described in detail in this paper. A suitable thin sputtered seed layer for the plating process was studied and developed; this layer serves as a barrier against Cu and has good contact properties to both n+ and p+ Si. The sputtering of the various materials could cause damage to the underlying
passivation layer and to the Si at the cell level, leading to a lower open-circuit voltage (Voc) and pseudo fill factor (pFF). Reduction of this damage has made it possible to obtain IBC cells with efficiencies of up to 21.9%, measured over the full wafer area of 239cm2.

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